The present inventive concept described herein relates to semiconductor design technology, and more particularly, to logic circuits capable of level shifting.
The voltage levels of power supply voltages applied from external devices are decreasing with the trend toward a decrease in the power consumption of semiconductor memory devices. A circuit for shifting an external low-level power supply voltage to a high-level power supply voltage is required to secure the operational stability and driving force of an internal device. Such a circuit is called a level shifter.
Recently, a continuing effort is being made to provide high integration and miniaturization in the semiconductor technology. However, using a level shifter to connect two logic units operating at different voltage levels may increase the occupied circuit area. It is desirable to provide a level shifting capability while minimizing an increase in the circuit occupation area.